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d s ac in dc out optional smart ac sense + peakswitch pi-3995-051006 d s en/uv bp figure 1. typical peak power application. product highlights ecosmart ? C extremely energy-effcient ? standby output power 0.6 w for 1 w input (high line) ? sleep mode power 2.4 w at 3 w input (high line) ? no-load consumption < 200 mw at 265 vac input ? surpasses california energy commission (cec), energy star, and eu requirements peakswitch features reduce system cost ? delivers peak power of up to three times maximum continuous output power ? 277 khz operation during peak power signifcantly reduces transformer size ? programmable smart ac line sensing provides latching shutdown during short circuit, overload and open loop faults, and prevents glitches during power down or brownout ? two external components reset latch on ac removal ? adaptive switching cycle on-time extension increases low line peak output power, minimizing bulk capacitor size ? adaptive current limit reduces output overload power ? frequency jittering reduces emi flter cost ? tight i 2 f tolerances and negligible temperature variation of key parameters ease design and lower cost ? accurate hysteretic thermal shutdown with automatic recovery provides complete system level overload protection and eliminates need for manual reset better system cost/performance over rcc & discrete ? simple on/off control C no loop compensation needed ? very low component count C higher reliability and single side printed circuit board ? high bandwidth provides fast turn on with no overshoot and excellent transient load response ? peak current limit operation rejects line frequency ripple ? built-in current limit and hysteretic thermal protection applications ? inkjet printer ? data storage, audio amplifer, dc motor drives description peakswitch is designed to address applications with high peak- to-continuous power ratio demands. the very high switching frequency during peak power loads and excellent load transient response reduce system cost as well as component count and size. peakswitch incorporates a 700 v power mosfet, oscillator, high voltage switched current source for startup, current limit, february 2007 table 1. notes: 1. typical continuous power in a non-ventilated enclosed adapter measured at +50 c ambient. 2. typical peak power for a period of 100 ms and a duty cycle of 10% in a non-ventilated enclosed adapter measured at +50 c (see key applications section for details). 3. see part ordering information. and thermal shutdown onto a monolithic device. in addition, these devices incorporate auto-restart, line under-voltage sense and frequency jittering. an innovative design minimizes audio frequency components in the simple on/off control scheme to practically eliminate audible noise with standard varnished transformer construction. output power table product 3 230 vac 15% 85-265 vac adapter cont. 1 adapter peak 2 adapter cont. 1 adapter peak 2 pks603 p 13 w 32 w 9 w 25 w pks604 p 23 w 56 w 16 w 44 w pks604 y/f 35 w 56 w 23 w 44 w pks605 p 31 w 60 w 21 w 44 w pks605 y/f 46 w 79 w 30 w 58 w pks606 p 35 w 66 w 25 w 46 w pks606 y/f 68 w 117 w 45 w 86 w pks607 y/f 75 w 126 w 50 w 93 w pks603-607 peakswitch ? family enhanced, energy-effcient, off-line switcher ic with super peak power performance
pks603-607 rev. i 02/07 2 figure 2. functional block diagram. figure 3. pin confguration. pin functional description drain (d) pin: the power mosfet drain connection provides internal operating current for both startup and steady-state operation. bypass (bp) pin: a 0.33 f external bypass capacitor for the internally generated 5.8 v supply is connected to this pin. in typical applications, this pin must be externally supplied via a bias winding. enable/under-voltage (en/uv) pin: this pin has dual functions: enable input and line under-voltage sense. during normal operation, switching of the power mosfet is controlled by this pin. mosfet switching is disabled when a current greater than 240 a is drawn from this pin. this pin may also sense line under-voltage conditions through either an external resistor connected to the dc line voltage or an ac sense circuit. source (s) pin: this is the mosfet source connection for high voltage return and control circuit common. pi-3940-040606 clock oscilla to r 5.8 v 4.8 v ground (gnd) (y & f package only) source (s) s r q dc max byp ass (bp) + - v i limi t fa ul t present current limit comp ara to r enable leading edge blanking thermal shutdown + - drain (d) regula to r 5.8 v byp ass pi n under-vol t age 1.0 v + v t enable/ under- vo lt age (en/uv) q 240 a 25 a line under-vol t age reset la tch off/ aut o- rest art counter on time ext jitter 1.0 v 6.3 v current limit st at e machine/ adaptive current limit pi-3941-031506 t ab internally connected to source pin y package (t o-220-7c) d s en/uv s s 1 bp 3 en/uv 2 gnd 5 nc 4 s 7 d 1 bp 3 en/uv 2 gnd 5 nc 4 s 7 d bp p package (dip-8c) f package (t o-262-7c) 8 5 7 1 4 2 s 6 ground (gnd) pin (y or f package only): this is the signal ground for the bypass capacitor and optocoupler.
pks603-607 rev. i 02/07 3 figure 4. frequency jitter. peakswitch functional description peakswitch integrates a 700 v power mosfet switch with a power supply controller on the same die. unlike conventional pulse width modulation (pwm) controllers, peakswitch uses a simple on/off control to regulate the output voltage. the controller consists of an oscillator, enable circuit (sense and logic), current-limit state machine, 5.8 v regulator, bypass pin under-voltage circuit, over- temperature protection, current limit circuit, and leading edge blanking. peakswitch incorporates additional circuitry for adaptive current limit, line under-voltage sense, programmable smart line sense, auto-restart, adaptive switching cycle on-time extension, and frequency jitter. figure 2 is a functional block diagram of the devices most important features. oscillator the typical oscillator frequency is internally set to an average of 277 khz. two signals are generated from the oscillator: the maximum duty cycle (dc max ) signal and the clock signal that indicates the beginning of each cycle. the oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 16 khz peak-to-peak, to minimize emi emission. the modulation rate of the frequency jitter is set to 1.1 khz to optimize emi reduction for both average and quasi-peak emissions. the frequency jitter should be measured with the oscilloscope triggered at the falling edge of the drain waveform. the waveform in figure 4 illustrates the frequency jitter. enable input and current-limit state machine the enable input circuit at the en/uv pin consists of a low impedance source follower output set at 1.0 v. the current through the source follower is limited to 240 a. when the current out of this pin exceeds 240 a, a low logic level (disable) is generated at the output of the enable circuit. this enable circuit output is sampled at the beginning of each cycle on the rising edge of the clock signal. if high, the power mosfet is turned on for that cycle (enabled). if low, the power mosfet remains off (disabled). since the sampling is done only at the beginning of each cycle, subsequent changes in the en/uv pin voltage or current during the remainder of the cycle are ignored. the current-limit state machine reduces the current limit by discrete amounts at light loads when peakswitch is likely to switch in the audible frequency range. the lower current limit raises the effective switching frequency above the audio range and reduces the transformer fux density, including the associated audible noise. the state machine monitors the sequence of en/uv pin voltage levels to determine the load condition and adjusts the current limit level accordingly in discrete amounts. under most operating conditions (except when close to no-load), the low impedance of the source follower keeps the voltage on the en/uv pin from going much below 1.0 v in the disabled state. this improves the response time of the optocoupler that is usually connected to this pin. 5.8 v regulator and 6.3 v shunt voltage clamp the 5.8 v regulator charges the bypass capacitor connected to the bypass pin to 5.8 v by drawing a current from the voltage on the drain pin whenever the mosfet is off. the bypass pin is the internal supply voltage node. when the mosfet is on, the peakswitch operates from the energy stored in the bypass capacitor. the voltage on the drain pin powers the bypass during start-up. there is a 6.3 v shunt regulator clamping the bypass pin at 6.3 v when current is provided through an external resistor from the bias winding in normal operation. powering the peakswitch device in this way minimizes no-load consumption to about 150 mw at 265 vac. note that a bias winding must be used to power the device. see key application considerations section for details. bypass pin under-voltage the bypass pin under-voltage circuitry disables the power mosfet when the bypass pin voltage drops below 4.8 v. once the bypass pin voltage drops below 4.8 v, it must rise back to 5.8 v to enable (turn on) the power mosfet. over temperature protection the thermal shutdown circuitry senses the die temperature. the threshold is typically set at 142 c with 75 c hysteresis. when the die temperature rises above this threshold, the power mosfet is disabled and remains disabled until the die temperature falls by 75 c, at which point it is re-enabled. a large 60 0 0 2.5 5 285 khz 269 khz v drai n ti me ( s) pi-3942-022806 50 0 40 0 30 0 20 0 10 0 0
pks603-607 rev. i 02/07 hysteresis of 75 c (typical) is provided to prevent overheating of the pc board during a continuous fault condition. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the power mosfet is turned off for the remainder of that cycle. the current limit state machine reduces the current limit threshold by discrete amounts under medium and light loads. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and secondary-side rectifer reverse recovery time will not cause premature termination of the mosfet conduction portion of the switching cycle. during startup and fault conditions, the controller prevents excessive drain currents by reducing the switching frequency. adaptive current limit when switching in the full current limit state, a skipped cycle followed by a cycle that terminates at the full current limit implies that the line voltage is at high line. under this condition, adaptive current limit reduces the full current limit level by approximately 10% in order to reduce output overload power. the next skipped cycle disables the adaptive current limit condition and restores the full current limit level. line under-voltage sense circuit the line under-voltage circuit prevents startup below the programmed input voltage by connecting an external resistor from either the dc line or from an ac sense circuit (see figure 1) to the en/uv pin. the complete function is described in the fow chart shown in figure 5. during power up or when the switching of the power mosfet is disabled in auto-restart, the current fowing into the en/uv pin must exceed 25 a to initiate switching of the power mosfet. during power up, once the threshold is exceeded, the bypass pin must charge from 4.8 v to 5.8 v before mosfet switching is initiated. the line under-voltage circuit also detects when there is no external resistor connected to the en/uv pin (less than ~1 a into pin). in this case, the line under-voltage function is disabled and the device operates with a normal auto-restart function. programmable smart ac line sense when an external ac sense circuit is used (see figure 1), the line under-voltage sense circuit can be used to determine the reason for a loss of feedback signal at the en/uv pin. in the event of a fault condition such as output overload, output short circuit, or an open loop condition, the power mosfet switching is disabled after the en/uv pin is not pulled low for 30 ms. if the ac line is present (i en > 25 a) at the time switching is disabled, 1. startup pi-4014-062305 2. uv resistor present? ye s ye s ye s no no no no ye s ye s no 3. ac input present? (i en >25 a) 4. start switching 5. no feedback >30 ms? 6. stop switching 7. ac input present? (i en >25 a) 8. reset a/r latch 9. start switching 10. no feedback >30 ms? 11 . stop switching (for 5 s) note: normal operatio n (no fault present) is denoted by looping with a ?no? response at decision box 5 or 10 . figure 5. peakswitch line sense function flow chart.
pks603-607 rev. i 02/07 5 v drai n v en clock d drai n i max pi-2749-050301 figure 7. peakswitch operation at near maximum loading. v drai n v en clock d drai n i max pi-2667-090700 figure 6. peakswitch auto-restart operation. the line under-voltage sense circuit prevents a restart attempt until the ac input voltage is removed (i en < 25 a). then the internal auto-restart latch is reset and the power mosfet switching will resume once the ac input voltage is applied again (i en > 25 a). this effectively provides a latching shutdown function with ac reset during such a fault condition. when a brownout or line sag occurs, output regulation may be lost and the en/uv pin will receive no feedback (it is pulled low). after 30 ms of no feedback, mosfet switching is disabled. since the ac line is abnormally low (i en < 25 a) mosfet switching remains disabled until normal line voltage is restored. the power mosfet switching will resume once the ac input returns to normal (i en > 25 a). this effectively disables the latching shutdown function during such a condition. auto-restart (uv resistor not present) in the event of a fault condition such as output overload, output short circuit or an open loop condition, peakswitch enters into auto-restart operation. an internal counter clocked by the oscillator is reset every time the en/uv pin is pulled low. when the en/uv pin receives no feedback for 30 ms, the power mosfet switching is disabled for 5 seconds (150 ms for the frst auto-restart event). the auto-restart alternately enables and disables the switching of the power mosfet until the fault condition is removed. figure 6 illustrates auto-restart circuit operation in the presence of an output short circuit. adaptive switching cycle on-time extension adaptive switching cycle on-time extension keeps the mosfet on until current limit is reached, instead of terminating after the dc max signal goes low. this on-time extension is adaptive because it only occurs after the enable pin has been high for approximately 750 s, a condition that would arise if the pi-3943-031506 0 5 1 0 t ime (s) 0 5 0 10 100 200 300 v drain v dc-outpu t peak output power was required in low line conditions. on-time extension is disabled during the startup of the power supply. peakswitch operation peakswitch devices operate in the current-limit mode. when enabled, the oscillator turns the power mosfet on at the beginning of each cycle. the mosfet is turned off when the current ramps up to the current limit or when the dc max limit is reached. since the highest current limit level and frequency figure 8. peakswitch operation at moderately heavy loading.
pks603-607 rev. i 02/07 6 figure 11. peakswitch power up with optional external uv resistor (4 m w ) connected to en/uv pin. pi-2661-072400 v drai n v en clock d drai n i max figure 10. peakswitch operation at very light loading. of a peakswitch design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. if the chosen peakswitch family member is appropriate for the power level, the current in the calculated inductance will ramp up to current limit before the dc max limit is reached. enable function peakswitch senses the en/uv pin to determine whether or not to proceed with the next switching cycle as described earlier. the sequence of cycles is used to determine the current limit. once a cycle is started, it always completes the cycle (even when the en/uv pin changes state half way through the cycle). this operation results in a power supply in which the output voltage ripple is determined by the output capacitor, amount of energy per switch cycle and the delay of the feedback. the en/uv pin signal is produced on the secondary by comparing the power supply output voltage with a reference voltage. the en/uv pin signal is high when the power supply output voltage is less than the reference voltage. in a typical implementation, the en/uv pin is driven by an optocoupler. the collector of the optocoupler transistor is connected to the en/uv pin and the emitter is connected to the source pin. the optocoupler led is connected in series with a zener diode across the dc output voltage to be regulated. when the output voltage exceeds the target regulation voltage level (optocoupler led voltage drop plus zener voltage), the optocoupler led will start to conduct, pulling the en/uv pin figure 9. peakswitch operation at medium loading. pi-2377-091100 v drai n v en clock d drain i max low. the zener diode can be replaced by a tl431 reference circuit for improved accuracy. on/off operation with current-limit state machine the internal clock of the peakswitch runs all the time. at the beginning of each clock cycle, it samples the en/uv pin to decide whether or not to implement a switch cycle, and based on the sequence of samples over multiple cycles, it determines the appropriate current limit. at high loads, when the en/uv pin is high (less than 240 a out of the pin), a switching cycle with the full current limit occurs. at lighter loads, when en/uv is high, a switching cycle with a reduced current limit occurs. pi-4331-031506 0 5 1 0 t ime (ms) 0 100 200 0 300 5 0 100 200 v dc-input v byp ass v drain
pks603-607 rev. i 02/07 7 figure 13. normal power down timing (without uv). figure 14. slow power down timing with optional external (4 m w ) uv resistor connected to en/uv pin. figure 12. peakswitch power up without optional external uv resistor connected to en/uv pin. at maximum peak load, peakswitch will conduct during nearly all of its clock cycles (figure 7). at the rated continuous load, it will skip additional cycles in order to maintain voltage regulation at the power supply output (figure 8). at medium loads, cycles will be skipped and the current limit will be reduced (figure 9). at very light loads, the current limit will be reduced even further (figure 10). only a small percentage of cycles will occur to satisfy the internal power consumption of the power supply at no-load. the response time of the on/off control scheme is very fast compared to normal pwm control. this provides tight regulation and excellent transient response. pi-2395-030801 0 2.5 5 ti me (s) 0 100 200 400 300 0 100 200 v dc-input v drain power up/down the peakswitch requires only a 0.33 f capacitor on the bypass pin. because of its small size, the time to charge this capacitor is kept to an absolute minimum, typically less than 1.5 ms. due to the fast nature of the on/off feedback, there is no overshoot at the power supply output. when an external resistor is connected from the positive dc input to the en/uv pin, the power mosfet switching will be delayed during power up until the dc line voltage exceeds the threshold (100 v). figures 11 and 12 show the power up timing waveform in applications with and without an external resistor (4 m w ) connected to the en/uv pin. during power down, when an external resistor is used, the power mosfet will switch for 30 ms after the output loses regulation. the power mosfet will then remain off without any glitches since the under-voltage function prohibits restart when the line voltage is low. figure 13 illustrates a typical power-down timing waveform. figure 14 illustrates a very slow power-down timing waveform as in standby applications. an external resistor is connected to the en/uv pin in this case to prevent unwanted restarts. current limit operation each switching cycle is terminated when the drain current reaches the current limit of the peakswitch . current limit operation provides good line ripple rejection. bypass pin capacitor the bypass pin uses a small 0.33 uf ceramic capacitor for decoupling the internal power supply. pi-2348-030801 0 .5 1 ti me (s) 0 100 200 300 0 100 200 400 v dc-input v drain modifying current schematic pi-4332-031506 0 5 1 0 t ime (ms) 0 100 200 0 300 5 0 100 200 v dc-input v byp ass v drain
pks603-607 rev. i 02/07 8 application example the circuit shown in figure15 is a low cost, high effciency, fyback power supply designed to provide a 30 v, 1.06 a continuous, 2.7 a peak output from universal input using the pks606y. the supply features under-voltage lockout and smart ac sense with fast reset. latching overload, open loop, and hysteretic thermal shutdown protect both the supply and load under fault conditions while high effciency (>80%) and very low no-load consumption (<200 mw at 230 vac) meets both active and standby effciency requirements. output regulation is accomplished using a simple zener reference and opto coupler feedback. components c1, c2, c3, c10, c17, c19, r15, l1 and l2 provide common mode and differential mode emi fltering. resistors r1 and r2 discharge c3 when ac power is removed to prevent electric shock from touching the ac input. thermistor rt1 limits the peak inrush current when ac is frst applied. the rectifed and fltered input voltage is applied to the primary winding of t1. the other side of the transformer primary is driven by the integrated mosfet in u1. diode d6, c5, r3, r4, and vr1 clamp the u1 drain voltage to safe levels. use of a fast diode (500 ns) vs ultrafast for d6 increases power supply effciency by recovering some of the clamp energy. a slow or standard recovery diode must not be used due to the high switching frequency (a slow diode will not recover fast enough under startup or output faults and therefore fail due to excess dissipation). the use of a zener in series with r3 compared to a standard rcd clamp optimizes both emi and energy effciency. components d5, c7, and r5-6 provide ac line and under- voltage sensing for peakswitch u1. by providing a separate rectifed voltage across c7 which is independent from the load condition, rather than using the main input capacitor, allows peakswitch to distinguish the cause of loss of regulation. it also provides fast reset when the ac input is removed, should latching shutdown be triggered. connecting r5 and r6 to c4 would still provide under-voltage lockout but after a fault the user would have to wait for c4 to discharge before the supply would reset. resistor r16 provides a small amount of bias to the u1 enable/under-voltage pin to retain the under- voltage lockout function during brown-out conditions. with r5 and r6 present, switching is inhibited until the current into the en/uv pin exceeds 25 a. this allows the startup voltage to be programmed within the normal operating input voltage range, preventing glitching of the output under abnormal, low voltage conditions and also on removal of the ac input. under a fault condition, for example an output short circuit or broken feedback loop, if the line voltage is within the normal range ( > 25 a into the en/uv pin) the peakswitch will latch t1 ee25 j1 l pe n 30 v @ 1.07 a cont. 2.7 a peak rtn d5 1n4007 d6 fr106 d10 uf4003 d8 stps3150 d9 1n4148 d7 1n4148 u2 pc817x4 q2 fs202da j3 pcb term 18 awg rtn connected to pe via flying lead q1 2n3906 d1-d4 1n4007 l1 5.3 mh l2 5.3 h r2 1.3 m ? r1 1.3 m ? r15 2.2 ? r4 22 ? 1/2 w r3 10 k ? 1/2 w r5 2.2 m ? r6 2.4 m ? r16 2.7 m ? r7 4.7 k ? r12 1 k ? r13 1 k ? r14 100 ? r11 3 k ? r10 1.5 k ? r9 0.33 ? 2 w r8 68 ? 1/2 w c3 680 nf x1 c1-c2 100 pf 250 vac c17 4.7 nf 1 kv c6 47 f 35 v c15 100 nf 50 v c16 100 nf c12 330 f 50 v c10 1 nf 250 vac c11 330 pf u1 pks606y c13 47 f 16 v c14 220 nf 50 v c7 100 nf 400 v c8 220 nf 50 v c5 2.2 nf 1 kv vr1 1n4764a 100 v vr2 1n5255b 28 v vr3 1n5258b 36 v 1 9,10 7,8 4 5 3 2 c4 150 f 400 v f1 3.15 a rt1 10 ? pi-4170-060706 t o peakswitch c19 1 nf, 250 vac d s en/uv bp gnd figure 15. peakswitch pks606y, 32 w continuous, 81 w peak, universal input power supply.
pks603-607 rev. i 02/07 off the power supply. this protects the load and supply from a continuous fault condition. removing the ac input resets this condition. the output voltage is determined by the zener diode vr2, the voltage drop across r12 and the forward drop of d9 and the led of optocoupler u2. resistor r13 provides bias current through d9 and vr2, to ensure that vr2 is operating close to its knee voltage, while r12 sets the overall gain of the feedback loop. capacitor c15 boosts high frequency loop gain to help distribute the enabled switching cycles and reduce pulse grouping. when the output voltage exceeds the feedback threshold voltage, current will fow in the optocoupler led, causing current fow in the transistor of the optocoupler. when this exceeds the enable pin threshold current the next switching cycle is inhibited, as the output voltage falls (below the feedback threshold) a conduction cycle is allowed to occur and by adjusting the number of enabled cycles output regulation is maintained. as the load reduces the number of enabled cycles decreases, lowering the effective switching frequency and scaling switching losses with load. this provides almost constant effciency down to very light loads, ideal for meeting energy effciency requirements. peakswitch device u1 is supplied from an auxillary winding on the transformer which is rectifed and fltered by d7 and c6. resistor r7 provides approximately 2 ma of supply current into the bypass pin capacitor c8. during startup or fault conditions when the bias voltage is low, the bypass pin is supplied from a high voltage current source within u1, eliminating the need for separate startup components. components q1-2, r9-11, r14, c13, c16, and vr3 form an overvoltage and overcurrent protection circuit. an output overvoltage or overcurrent condition fres scr q2, clamping the output voltage and forcing peakswitch u1 into latching shutdown after 30 ms. the low pass flter formed by r10 and c13 adds a delay to the over-current sense. the shutdown condition can be reset by briefy removing ac power for ~3 seconds (maximum). the latching function within peakswitch signifcantly reduces the size of the scr and output rectifer, d8, as the short circuit current only fows for 50 ms before the supply latches off. this design meets en55022 class b conducted emi with >10 db margin even with the output rtn directly connected to earth ground. key application considerations peakswitch design considerations output power table the data sheet maximum output power table (table 1) represents the maximum practical continuous output power level that can be obtained under the following assumed conditions: 1. the minimum dc input voltage is 100 v or higher for 85 vac input, or 220 v or higher for 230 vac input or single 100/115 vac with a voltage doubler. 2. effciency of 70% for y/f packaged devices, 75% for p packaged devices at 85-265 vac, 75% for 230 vac input all packages 3. minimum datasheet value of i 2 f 4. transformer primary inductance tolerance of 10% 5. refected output voltage (v or ) of 135 v 6. voltage only output of 15 v with an ultra fast pn rectifer diode 7. continuous conduction mode operation with transient k p * value of 0.25 8. suffcient heatsinking is provided, either externally (y/f packages) or through an area of pc board copper (p package) to keep the source pin or tab temperature at or below 110 c. 9. device ambient temperature of 50 c for open frame designs and 40 c for sealed adapters * below a value of 1, k p is the ratio of ripple to peak primary current. to prevent reduced power capability due to premature termination of switching cycles, a transient k p limit of 0.25 is recommended. this avoids the initial current limit (i init ) being exceeded at mosfet turn on. peak vs. continuous power peakswitch devices have current limit values that allow the specifed peak power values in the power table. with suffcient heatsinking, these power levels could be provided continuously, however this may not be practical in many applications. peakswitch is optimized for use in applications that have short duration, high peak power demand, but a signifcantly lower continuous or average power. typical ratios would be p peak 2 p ave . the high switching frequency of peakswitch allows a small core size to be selected to deliver the peak power, but the short duration prevents the transformer winding from overheating. as average power increases, it may be necessary to select a larger transformer to allow increased copper area for the windings based on the measured transformer temperature. the power table provides some guidance between peak power and continuous power in sealed adapters, however specifc applications may differ. for example, if the peak power condition is very low duty cycle, say a 2 second peak occurring only at power up to accelerate a hard disk drive, then the transformers thermal rise is only a function of the continuous power. however, if the peak power occurs every 200 ms for 50 ms then it would need to be considered. in all cases, the acceptable temperature rise of the peakswitch and transformer should be verifed under worst case ambient and load conditions.
pks603-607 rev. i 02/07 10 figure 16 shows how to calculate the average power requirements for a design with two different peak load conditions. where p x are the different output power conditions, t x are the durations of each peak power condition, and t is the period of one cycle of the pulse load condtion. audible noise the cycle skipping mode of operation used in peakswitch can generate audio frequency components in the transformer. to limit this audible noise generation, the transformer should be designed such that the peak core fux density is below 3000 gauss (300 mt). following this guideline and using the standard transformer production technique of dip varnishing practically eliminates audible noise. vacuum impregnation of the transformer should not be used due to the high primary capacitance and increased losses that result. ceramic capacitors that use dielectrics such as z5u, when used in clamp circuits, may also generate audio noise. if this is the case try replacing them with a capacitor having a different type of dielectric or construction, for example a flm type capacitor. maximum flux density a maximum value of 3000 gauss during normal operation is recommended to limit the maximum fux density under start up and output short circuit. under these conditions the output voltage is low and little reset of the transformer occurs during the mosfet off time. this allows the transformer fux density to staircase above the normal operating level. a value of 3000 gauss at the peak current limit of the selected device, together with the built in protection features of peakswitch provides suffcient margin to prevent core saturation under startup or output short circuit conditions. optocoupler ctr to minimize the delay introduced by the optocoupler, it is recommended that a high (300-600%) ctr optocoupler is used in peakswitch designs. bias winding all peakswitch designs must use a bias winding to feed operating current into the bypass pin once the supply is operational. it is recommended that the value of the resistor from the bias winding to the bypass pin be selected such that it supplies the same current as the maximum datasheet drain supply current (i s2 ) for the specifc device being used. peakswitch layout considerations see figure 17 for a recommended circuit board layout for peakswitch. single point grounding devices in y and f packages have separate return pins for the mosfet source (s) and the controller (gnd) connections which are internally connected. therefore connecting these pins on the pc board is not recommended. devices in the p package do not have separate return pins, but in both cases the low current feedback signals and ic decoupling, high mosfet current and bias winding primary return connection should route through separate traces to the kelvin connection. the bias winding return connection is treated separately, even though it carries low current. to route high currents away from the device when the supply is subjected to line surge transients, the bias winding should be returned directly to the input bulk capacitor. bypass capacitor (c bp ) the bypass pin capacitor should be located as close as possible to the bypass and source pins. primary loop area the area of the primary loop that connects the input flter capacitor, transformer primary and peakswitch together should be kept as small as possible. primary clamp circuit a clamp is used to limit the peak voltage on the drain pin at turn off. this can be achieved by using an rcd clamp or a zener (~200 v) and diode clamp across the primary winding. in all cases to minimize emi care should be taken to minimize the circuit path from the clamp components to the transformer and peakswitch. figure 16. continuous (average) output power calculation example. pi-4329-030906 p 3 power (w) t ime (t) t ? t 1 ? t 2 p 2 p 1
pks603-607 rev. i 02/07 11 figure 17. recommended layout for peakswitch in (a) p and (b) y/f packages. - + input filter capacitor heat sink safety spacing opto- coupler + - dc out t r a n s f o r m e r sec d gnd pi-4327-031706 to p view hv nc en/uv output rectifier output filter capacitor maximize hatched copper areas ( ) for optimum heatsinking y1- capacitor pri pri bias bias bp c bp to p view pi-4326-060706 opto- coupler + - hv + - dc out input filter capacitor output rectifier safety spacing t r a n s f o r m e r pri sec bias bias peakswitch output filter capacitor maximize hatched copper areas ( ) for optimum heatsinking bp en/uv y1- capacitor s s s s pri c bp d (a) (b)
pks603-607 rev. i 02/07 12 thermal considerations for the p package, the four source pins are internally connected to the ic lead frame and provide the main path to remove heat from the device. therefore, all the source pins should be connected to a copper area underneath the peakswitch to act not only as a single point ground, but also as a heatsink. as this area is connected to the quiet source node, it should be maximized for good heatsinking. similarly, for axial output diodes, maximize the pcb area connected to the cathode. y-capacitor the placement of the y-type cap should be directly from the primary input flter capacitor positive terminal to the common/ return terminal of the transformer secondary. if a second y- type cap is required from primary to secondary return, connect the primary side directly to the negative terminal of the input capacitor. such a placement will route high magnitude common mode surge currents away from the peakswitch device. note C if an input (c, l, c) emi flter is used, then the inductor in the flter should be placed between the negative terminals on the input flter capacitors. optocoupler place the optocoupler physically close to the peakswitch to minimize the primary side trace lengths. keep the high current high voltage drain and clamp traces away from the optocoupler to prevent noise pick up. output diode for best performance, the area of the loop connecting the secondary winding, the output diode and the output flter capacitor should be minimized. in addition, suffcient copper area should be provided at the anode and cathode terminal of the diode for heatsinking. a larger area is preferred at the quite cathode terminal. a large anode area can increase high frequency radiated emi. quick design checklist as with any power supply design, all peakswitch designs should be verifed on the bench to make sure that component specifcations are not exceeded under worst case conditions. the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that the v ds does not exceed 650 v at highest input voltage and peak (overload) output power. the 50 v margin to the 700 v bv dss specifcation allows margin for design variation. 2. maximum drain currents C verify the simultaneous drain voltage and current levels are within the curve provided in figure 29 under worst case conditions. typically this occurs at start up (and during an output short circuit), highest input line voltage and maximum ambient temperature. when making this measurement using a current probe, to monitor the drain current, ensure the results are corrected for the 10-20 ns current probe delay. 3. maximum drain current C at maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms show no signs of transformer saturation. if the transformer shows signs of saturation, it should be redesigned with a lower fux density, or a higher quality core material should be used. to prevent false triggering of the current limit, verify the leading edge current spike event is below i init(min) at the end of the t leb(min) . under all conditions, the maximum drain current should be below the absolute maximum limit specifed in the absolute maximum ratings section. 4. thermal check C at specifed maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifcations are not exceeded for peakswitch , transformer, output diode and output capacitors. enough thermal margin should be allowed for part-to-part variation of the r ds(on) of peakswitch as specifed in the data sheet. under low line, maximum power, a maximum peakswitch source pin or tab temperature of 110 c is recommended to allow for these variations. design tools up-to-date information on design tools can be found at the power integrations web site: www.powerint.com.
pks603-607 rev. i 02/07 13 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units control functions output frequency f osc t j = 25 c see figure 4 average 250 277 304 khz peak-peak jitter 16 maximum duty cycle dc max s1 open 62 65 68 % en/uv pin turn off threshold current i dis -350 -240 -200 a en/uv pin voltage v en i en/uv = -125 a 0.4 1.0 1.5 v i en/uv = 25 a 1.3 2.0 2.7 drain supply current i s1 v en/uv = 0 v 350 475 600 a i s2 en/uv open (mosfet switching) see note a, b pks603 460 570 690 pks604 600 725 870 pks605 700 875 1050 pks606 950 1175 1400 pks607 1160 1430 1700 bypass pin charge current i ch1 v bp = 0 v, t j = 25 c see note c pks603-604 -7.5 -5.0 -2.5 ma pks605-607 -10.0 -6.6 -3.2 i ch2 v bp = 4 v, t j = 25 c see note c pks603-604 -4.5 -3.0 -1.5 pks605-607 -6.5 -4.5 -2.5 absolute maximum ratings (1,) drain voltage .................................. ..............-0.3 v to 700 v drain peak current: ....................... ...... 2 i limit (typical) (5) en/uv voltage ....................................................-0.3 v to 9 v en/uv current .................................................... ....... 100 ma bypass voltage .................................................. -0.3 v to 9 v storage temperature ......................................-65 c to 150 c operating junction temperature (2) .................-40 c to 150 c lead temperature (3) ................ ....................................... 260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. maximum ratings specifed may be applied one at a time, without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. 5. peak drain current is allowed while the drain voltage is simultaneously less than 400 v. see also figure 29. thermal impedance thermal impedance: y/f package: ( q ja ) (1) ........................................80 c/w ( q jc ) (2) ..........................................2 c/w p package: ( q ja ) .....................70 c/w (3) ; 60 c/w (4) ( q jc ) (5) ..................................... 10 c/w (5) notes: 1. free standing with no heatsink. 2. measured at the back surface of tab. 3. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 4. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 5. measured on the source pin close to plastic interface.
pks603-607 rev. i 02/07 1 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units control functions (cont.) bypass pin shunt regulator voltage v bp(sh) see note d 6.0 6.3 6.7 v bypass pin voltage v bp 5.5 5.8 6.15 v bypass pin voltage hysteresis v bph 0.8 1.0 1.3 v en/uv pin line under-voltage threshold i luv t j = 25 c 22.5 25 27.5 a circuit protection current limit i limit pks603 p t j = 25 c di/dt = 200 ma/ s see note e 0.75 0.81 0.87 a pks604 p/y/f t j = 25 c di/dt = 290 ma/ s see note e 1.35 1.45 1.55 pks605 p t j = 25 c di/dt = 290 ma/ s see note e 1.35 1.45 1.55 pks605 y/f t j = 25 c di/dt = 325 ma/ s see note e 1.76 1.89 2.02 pks606 p t j = 25 c di/dt = 255 ma/ s see note e 1.40 1.51 1.62 pks606 y/f t j = 25 c di/dt = 660 ma/ s see note e 2.60 2.80 3.00 pks607 y/f t j = 25 c di/dt = 800 ma/ s 2.79 3.00 3.21 power coeffcient i 2 f pks603 p t j = 25 c di/dt = 200 ma/ s 164 182 204 a 2 khz pks604 p/y/f t j = 25 c di/dt = 290 ma/ s 524 582 652 pks605 p t j = 25 c di/dt = 290 ma/ s 524 582 652 pks605 y/f t j = 25 c di/dt = 325 ma/ s 890 989 1108 pks606 p t j = 25 c di/dt = 255 ma/ s 569 632 708 pks606 y/f t j = 25 c di/dt = 660 ma/ s 1955 2172 2433 pks607 y/f t j = 25 c di/dt = 800 ma/ s 2242 2493 2793
pks603-607 rev. i 02/07 15 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units circuit protection (cont.) initial current limit i init see figure 21 see note f 0.75 i limit(min) ma leading edge blanking time t leb t j = 25 c see note f 170 215 ns current limit delay t ild t j = 25 c see notes f, g 150 ns thermal shutdown temperature 135 142 150 c thermal shutdown hysteresis 75 c output on-state resistance r ds(on) pks603 i d = 81 ma t j = 25 c 7.8 9.0 w t j = 100 c 11.7 13.5 pks604 i d = 150 ma t j = 25 c 5.2 6.0 t j = 100 c 7.8 9.0 pks605 i d = 200 ma t j = 25 c 3.9 4.5 t j = 100 c 5.8 6.7 pks606 i d = 300 ma t j = 25 c 2.6 3.0 t j = 100 c 3.9 4.5 pks607 i d = 300 ma t j = 25 c 2.0 2.3 t j = 100 c 3.0 3.5 off-state drain leakage current i dss1 v bp = 6.2 v v en/uv = 0 v v ds = 560 v t j = 125 c see note h 200 a i dss2 v bp = 6.2 v v en/uv = 0 v v ds = 375 v t j = 50 c see note h 15 breakdown voltage bv dss v bp = 6.2 v, v en/uv = 0 v, see note i, t j = 25 c 700 v drain supply voltage 50 v output en/uv delay t en/uv see figure 20 5 s output disable setup time t dst 0.5 s
pks603-607 rev. i 02/07 16 notes: a. total current consumption is the sum of i s1 and i dss when en/uv pin is shorted to ground (mosfet not switching) and the sum of i s2 and i dss when en/uv pin is open (mosfet switching). b. since the output mosfet is switching, it is diffcult to isolate the switching current from the supply current at the drain. an alternative is to measure the bypass pin current at 6.1 v. c. see typical performance characteristics section for bypass pin startup charging waveform. d. bypass pin is externally supplied (bias winding). e. for current limit at other di/dt values, refer to figure 25. f. this parameter is derived from characterization. g. this parameter is derived from the change in current limit measured at 1x and 4x of the di/dt shown in the i limit specifcation. h. i dss1 is the worst case off state leakage specifcation at 80% of bv dss and maximum operating junction temperature. i dss2 is a typical specifcation under worst case application conditions (rectifed 265 v ac) for no-load consumption calculations. i. breakdown voltage may be checked against minimum bv dss specifcation by ramping the drain pin voltage up to but not exceeding minimum bv dss . j. auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). auto-restart on time is extended during startup and certain fault conditions because the controller reduces its oscillator clock frequency to prevent excessive drain currents. if excessive drain currents are still occuring half way through the auto-restart on time, output mosfet switching is disabled for the remainder of that auto-restart on time episode (if the line is not sensed) or the supply latches off (if the line is sensed and adequate line voltage is present). k. only applicable if no uv resistor is present at the en/uv pin. 5 s applies only if the preceding switching auto- restart event did not result in en/uv pin going low. in that event, the frst auto-restart off-time is 150 ms. parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units output (cont.) auto-restart on time t ar t j = 25 c see note j 30 ms auto-restart off time t aroff see note k 5 s
pks603-607 rev. i 02/07 17 figure 19. duty cycle measurement. figure 20. output enable timing. figure 18. peakswitch general test circuit. figure 21. current limit envelope. pi-4317-030606 0.33 f 10 v 50 v 470 w 5 w s2 470 w note: this test circuit is not applicable for current limit or output characteristic measurements. s d bp s s en/uv s 150 v s1 4 m w pi-2364-012699 en/uv t p t en/uv dc max t p = 1 f osc v drain (internal signal) 0.8 pi-4328-030806 t le b (blanking ti me ) i init(min ) i limit(min ) @ 100 c
pks603-607 rev. i 02/07 18 typical performance characteristics 1.1 1.0 0.9 -50 -25 0 2 5 5 0 7 5 100 125 150 junction t emperature ( c) breakdown v oltage (normalized to 25 c) pi-2213-012301 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1 2 3 4 normalized di/dt pi-4297-020806 normalized current limit figure 22. breakdown vs. temperature. figure 23. frequency vs. temperature. figure 25. current limit vs. di/dt. figure 24. standard current limit vs. temperature. figure 26. output characteristic. figure 27. c oss vs. drain voltage. 1.2 0.6 0.8 1.0 0 0.2 0.4 -50 -25 0 2 5 5 0 7 5 1 00 125 junction t emperature ( c) output frequenc y (normalized to 25 c) pi-4294-022806 1.2 0.6 0.8 1 0 0.2 0.4 -50 0 5 0 100 150 junction t emperature ( c) standard current limit (normalized to 25 c) pi-4295-02080 6 1.2 0.6 0.8 1.0 0 0.2 0.4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 0 4 drain v oltage (v ) drain current (a) pi-4307-09120 6 pks603 1.0 pks604 1.5 pks605 2.0 pks606 3.0 pks607 4.0 scaling factors: t j = 25 c t j = 100 c drain v oltage (v ) drain capacitance (pf) pi-4308-091206 0 100 200 300 400 500 600 1 10 100 1000 pks603 1.0 pks604 1.5 pks605 2.0 pks606 3.0 pks607 4.0 scaling factors:
pks603-607 rev. i 02/07 1 typical performance characteristics (cont.) figure 28. under-voltage threshold vs. temperature. 1.2 0.6 0.8 1 0 0.2 0.4 -50 0 5 0 100 150 junction t emperature ( c) under-v oltage theshold (normalized to 25 c) pi-4296-02080 6 figure 29. maximum allowable drain current vs. drain voltage. 2.5 1.5 2 0 1 0.5 0 600 50 0 40 0 30 0 20 0 100 800 70 0 drain v oltage (v ) drain current (normalized to t ypical i limi t ) pi-4330-03160 6
pks603-607 rev. i 02/07 20 part ordering information peakswitch product family series number package identifer p plastic dip-8c y plastic to-220-7c f plastic to-262-7c lead finish n pure matte tin (pb-free) pi-2644-122004 notes: 1. controlling dimensions are inches. millimeter dimensions are shown in parentheses. 2. pin numbers start with pin 1, and continue from left to right when viewed from the front. 3. dimensions do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15mm) on any side. 4. minimum metal to metal spacing at the package body for omitted pin locations is .068 in. (1.73 mm). 5. position of terminals to be measured at a location .25 (6.35) below the package body . 6. all terminals are solder plated. y07c pin 1 pin 7 mounting hole pa ttern .050 (1.27) .150 (3.81) .050 (1.27) .150 (3.81) .050 (1.27) .050 (1.27) .100 (2.54) .180 (4.58) .200 (5.08) pin 1 + .010 (.25) m .461 (1 1.71) .495 (12.57) .390 (9.91) .420 (10.67) .146 (3.71) .156 (3.96) .860 (21.84) .880 (22.35) .024 (.61) .034 (.86) .068 (1.73) min .050 (1.27) bsc .150 (3.81) bsc .108 (2.74) ref pin 1 & 7 7 typ . pin 2 & 4 .040 (1.02) .060 (1.52) .190 (4.83) .210 (5.33) .012 (.30) .024 (.61) .080 (2.03) .120 (3.05) .234 (5.94) .261 (6.63) .165 (4.19) .185 (4.70) .040 (1.02) .060 (1.52) .045 (1.14) .055 (1.40) .670 (17.02) ref . .570 (14.48) ref . to -220-7c pks 60 p n
pks603-607 rev. i 02/07 21 notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/85) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 3 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measured at package body . 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 sea ting plane -d- -t - p08c dip-8c pi-3933-100504 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum
pks603-607 rev. i 02/07 22 pi-2757-122004 notes: 1. controlling dimensions are inches. millimeter dimensions are shown in parentheses. 2. pin numbers start with pin 1, and continue from left to right when viewed from the front. 3. dimensions do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15mm) on any side. 4. minimum metal to metal spacing at the pack- age body for omitted pin locations is .068 inch (1.73 mm). 5. position of terminals to be measured at a location .25 (6.35) below the package body . 6. all terminals are solder plated. f07c pin 1 pin 7 mounting hole pa ttern .050 (1.27) .150 (3.81) .050 (1.27) .150 (3.81) .050 (1.27) .050 (1.27) .100 (2.54) .180 (4.58) .200 (5.08) pin 1 .010 (.25) m .326 (8.28) .336 (8.53) .390 (9.91) .420 (10.67) .795 (20.18) ref . .024 (.61) .034 (.86) .050 (1.27) bsc .150 (3.81) bsc .055 (1.40) .066 (1.68) pin 1 & 7 7 typ . pin 2 & 4 .040 (1.06) .060 (1.52) .190 (4.83) .210 (5.33) .012 (.30) .024 (.61) .080 (2.03) .120 (3.05) .165 (4.17) .185 (4.70) .040 (1.02) .060 (1.52) .045 (1.14) .055 (1.40) .595 (15.10) ref . .495 (12.56) ref . to -262-7c .068 (1.73) min
pks603-607 rev. i 02/07 23
pks603-607 rev. i 02/07 2 revision notes date f 1) final release data sheet. 3/06 g revised device symbol in figures 1 and 15 to be consistent with other pi documentation (added second ground connection). revised layout of figure 17 (pi-4326). 4/06 h revised grounding in figure 1 to match actual implementation. 6/06 i added pks607. 2/07 for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch , tinyswitch , linkswitch , dpa-switch , peakswitch , clampless , ecosmart , e-shield , filterfuse , stackfet , pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?copyright 2007, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasalespowerint.com china (shanghai) rm 807-808a pacheer commercial centre, 555 nanjing rd. west shanghai, p.r.c. 200041 phone: +86-21-6215-5548 fax: +86-21-6215-2468 e-mail : chinasalespowerint.com china (shenzhen) rm 2206-2207, block a, electronics science & technology bldg. 2070 shennan zhong rd. shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasalespowerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosalespowerint.com india #1, 14th main road vasanthanagar bangalore-560 052, india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasalespowerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: + 39-028-928-6009 e-mail: eurosalespowerint.com japan 1st bldg shin-yokohama 2-12-20 kohoku-ku, yokohama-shi, kanagawa ken, japan 222-0033 phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansalespowerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasalespowerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesalespowerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei 114, taiwan r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansalespowerint.com united kingdom 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-140 fax: +44 (0) 1252-727-689 e-mail: eurosalespowerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760

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